The invention relates to an address generation unit (AGU) and to a logic circuit incorporating an AGU.
Many different configurations of an AGU have been provided heretofore. However, they suffer from limited versatility in the range of possible addressing operations.
It is therefore an object of the invention to provide an AGU having a greater range of possible addressing operations, while also having a relatively small silicon area. Another object is to provide an AGU having a higher clock frequency and data throughput than conventional AGUs.
According to the invention, there is provided an address generation unit for a digital signal processor, the address generation unit comprising a digital addressing unit comprising:
a plurality of adders;
an input path connected to the adders;
selection multiplexers connected to the adder outputs; and
a control logic for controlling the adders and the multiplexers to operate with a configuration for each of
a plurality of addressing operations.
In one embodiment, the address generation unit further comprises a register file for providing parameter values for the digital addressing unit.
In another embodiment, the register file delivers order, stage, and displacement values to the digital addressing unit.
In a further embodiment, the register file provides an input to the digital addressing unit and receives an output from the digital addressing unit.
In one embodiment, a selection multiplexer is connected to a plurality of the adders and directly to the input path, and the selection multiplexer selects bits from its inputs to provide a combined output.
In one embodiment, the control logic selects bits from a second adder if there is a carry out from a first adder.
In one embodiment, the control logic delivers a mask signal to the first adder to ensure that the carry is propagated to carry out.
In another embodiment, the control logic directs signals to the adders and to the multiplexers for radix-4 increment and radix-4 decrement addressing operations.
In a further embodiment, the control logic directs a radix-4 addressing operation as follows:
directing the second adder to pre-compute +1 for radix-4 increment or to pre-compute xe2x88x921 for radix-4 decrement;
delivering a control signal to the first adder according to order and stage parameter values;
delivering a masking signal to the first adder to mask most significant bits (MSBs) to ensure that a carry is propagated to carry out;
controlling a selection multiplexer to provide an output comprising:
MSBs from the input signal;
middle bits from the output of the first adder; and
least significant bits (LSBs) from the output of the second adder if there is a carry out from the first adder, or alternatively from the input signal.
In one embodiment, an adder is connected at both its input and its output to a bit reverse block, and the bit-reverse block connected to the adder input is connected to the input path.
In one embodiment, the control logic delivers a second input to the adder according to the order value.
According to another aspect, the invention provides a digital signal processor comprising an address generation unit as defined above and a program control unit for delivering a control signal to the address generation unit for selection of the required addressing operation.